Embedded systems for particular purposes of usage are coming into wide use. The embedded systems have been applied by various field such as home electric apparatus, automobiles, etc. In an embedded system, the processor usually receives an interrupting signal from a control object and controls the apparatus by executing a processing in response to an interrupting signal generated.
FIG. 3 shows how the mode of processing executed by the processor updates in response to interruptions generated. When the processor receives interruption 1 at time t1 of a processing during an execution, it interrupts the running processing, and executes processing corresponding to the interruption 1. When return instruction signal (RET) is generated at time t2, the processor reopens the execution of the processing that has been interrupted upon receipt of the interruption 1. After that, the processor executes a processing corresponding to interruption 8 at time t3 to interrupt again the running processing when the processor receives new interruption 8 at time t3.
During execution in response to interruption 8, the processor receives interruption 1 at time t4 again, then executes the processing in response to interruption 1 to interrupt the running processing. Besides, during the execution responding to interruption 1, upon receiving interruption 2 at time t5, the processor executes a processing in response to the interruption 2. When the processing in response to the interruption 2 generates a return instruction RET at time T6, the processor reopens the processing being interrupted in response to interruption 1. The processor reopens the processing in response to interruption 8 when the reopened processing corresponding to interruption 1 generates a return instruction RET at time t7. When the processing corresponding to the interruption 8 generates a return instruction RET at time t8, the processor reopens the processing interrupted in order to execute the processing which responds to the interruption 8 at time t3.
In an embedded system, the processing corresponding to the interruptions is usually executed by the same memory sources. Therefore, in case where the processing by the processor proceed in a fashion as shown in FIG. 3, if the processing corresponding to the interruption 2 rewrites contents in a memory area used as data area and program area by the processing corresponding to the interruption 1 which was running just before, the data to be used for processing corresponding to the interruption 1 is destroyed. Then it occurs that the processing corresponding to interruption 1 to be reopened after time t7 is not executed correctly. In order to prevent such situation, it is preferred that the processing corresponding to each interruption is to be executed under memory protection to prohibit memory access outside the memory area previously designated for the processing in question.
The memory protection function is available in case where the OS designates the accessible memory area in the processing corresponding to each interruption. For example, in FIG. 3, upon receipt of an interruption 2 at time t5, the processor executes programs in the OS in which the processing corresponding to the interruption 2 is executed, after executing many programs including designation of accessible memory area in the processing corresponding to interruption 2 to be followed next. Besides, upon generating of the RET instruction at time t6 followed by reopening of the processing corresponding to the interruption 2, the programs of the OS are executed such that many programs including designation of the accessible memory area are executed followed by the processing corresponding to the interruption 1. The technique for the OS designating the accessible memory area etc. is disclosed in Patent Document 1, for example,
In this point, the plurality of interruptions input to the processor include such interruptions that should finish the processing within a predetermined time after generation, in other words those which should correspond to a processing having a high real time performance as demanded. In case where the OS should set up the memory protection for the processing that requires high real time performance, the OS must execute many processing including designation of accessible memory area after generation of interruption until the OS opens execution of processing corresponding to the instruction. Therefore, there is the possibility that the real time performance of the processing would fail, to degrade the responsibility of interruption.
In each processing, the fact that the designation of an accessible memory area is available means, in the all, that it is possible to access an arbitrary area of memory area in the processing. Therefore, the setting of the accessible memory area should be executed with the OS. However, and in this case, it is difficult to execute the memory protection with high response characteristics of the interruption. Based on this reason, in the systems demanding high real time characteristics, weight is given on the characteristic of high response, and, each processing corresponding to interruptions is executed without memory protection, i.e., without setting the memory area accessible by the OS, as shown in FIG. 3.
[Patent Document 1]
Japanese Patent Kokai Publication No.P2001-163309A